%related work

\subsection{Architectures for processors in emerging technologies}
Heterogeneous integration of CMOS with several emerging devices has been an active research area due to the shortcomings being exposed in conventional CMOS with technology scaling.
~\cite{ionescu-nems} has proposed the use of emerging technologies like Nano-Electro-Mechanical FETs and Tunnel FETs in integrated circuit logic. In this paper, we extend device level models to a complete processor-level abstraction, including logic and wire delay and power modeling.
The use of device-level heterogeneous multicores comprising of CMOS and TFET based processors has been explored in~\cite{islped11},~\cite{codes12} and~\cite{ieeemicro-tfet}. 
These papers mainly propose the use of simple, architecturally homogeneous multicores, with application mapping so as to minimize power under an iso-performance constraint or maximize performance in an iso-power scenario.
This paper explores design of 3D stacked processors comprising TFET and CMOS cores and explore different architectural tradeoff points under thermal and yield constraints.

\subsection{3D stacked architectures}
The authors in ~\cite{ionescu-3D} analyze various aspects of heterogeneous device integration in 3D technology. Our work, while based on this concept, extends this further by incorporating thermal and yield models as well as application mapping algorithms on heterogeneous 3D architectures. ~\cite{tullsen-3D} proposes the idea of \emph{Resource Pooling} across multiple stacked layers within a processor and efficiently allocating resources and tasks to each layer. Our work examines the viability of stacking processors on top of each other without folding individual cores which is an extremely complicated task due to wiring concerns.
 
\subsection{Heterogeneous architectures}
Heterogeneous Asymmetric Chip Multi Processors cores have been proposed in the past ~\cite{micro03, isca04} which deal with the varying demands from the applications in terms of Instruction Level Parallelism (ILP) and Thread Level Parallelism (TLP). 
These schemes decide the number of big (out-of-order) and small (in-order) cores statically. 
To circumvent this static techniques, there have been works ~\cite{morphcore}, ~\cite{corefusion} which dynamically transform the issue widths to cater to the sequential (ILP) and parallel(TLP) parts of the applications.
~\cite{corefusion} employs dynamically fusing the cores to form a large one core group to increase the performance of the sequential code.
These fusable cores can also execute parallel threads independently in isolation to speed up the parallel portions of the application.
This technique suffers from the overheads while reconfiguring like instruction cache flushes, data migration etc. which are circumvented in ~\cite{morphcore} by dynamically transforming an Out of order core in to SMT based in-order core.

\subsection{Architectural techniques for power and thermal aware execution}
Dreslinski, \emph{et. al}~\cite{NTC-UMich} proposed the concept of \emph{Near Threshold Computing} (NTC), where the processors are run at a voltage level close to $V_t$, so that it operates at a point where the power efficiency is the highest. 
By incorporating TFET cores into our system, the near-threshold voltage restriction is eliminated and a far wider range of operating points are available to the user.
\emph{Computational Sprinting} is another technique which can be used to improve the utilization of processors under power and thermal limitations~\cite{ieeemicro-sprinting}. In this paper, the authors briefly allow the processor to briefly exceed the processor power limitation by operating it at extremely high performance points for short periods of time. Our system allows for high performance CMOS cores to selectively run based on the application requirement, which covers most of the scenarios for which sprinting is required. It is also a more robust technique from the perspective of reliability and aging.

\subsection{Thermal-Aware application mapping on multicores}
%However, in addition to the operational inefficiencies of this method, the reliability in terms of soft error vulnerability is also affected adversely, making TFETs a better choice for operating in this design space~\cite{huichu-iedm12}.
In ~\cite{prometheus}, the authors propose PROMETHEUS, a heterogeneous multiprocessor SOC-based thermal-aware scheduling policies, such as TempoMP and TemPrompt.
Our techniques extend over a wide range of application domains and incorporated everywhere from embedded SOCs to high end server architectures.
~\cite{thermal-dvfs-asu} describes a thermal-aware DVFS algorithm for real-time applications running on a multicore, while~\cite{hhlee-3D-dvfs} proposes DVFS techniques on 3D multicores.
This paper examines general purpose applications with a large diversity in scaling behavior and memory utilization and attempts to optimize the thermally constrained performance on a device-level heterogeneous multicore, for the entire spectrum of application characteristics.
%These techniques though yield accurate prediction in temperature based on the current state of the core and use them for scheduling the tasks, they do not consider micro-architectural reconfiguration of the cores to achieve a better Energy Delay Product(EDP).
